TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 421

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.16.5.2 Printer Class Request
3.16.5.3 Vendor request (Class request)
bmRequestType
110000xxB
INT_SETUP interrupt.
is stored, and identify the request. If this request is a Vendor request, control the UDC
externally, and process the Vendor request.
and for the case where data phase is receiving (Control write).
UDC does not support “Automatic answer” of printer class request.
Processing of Class requests is the same as for vendor requests when answering
UDC does not support “Automatic answer” of Vendor requests.
According to INT_SETUP interrupt, access the register in which the device request
Below is an explanation for the case where data phase is transmitting (Control read),
bRequest, wValue, wIndex and wLength registers and process each request.
According to application, access Setup_Received register after request has been
identified.UDC must also be informed that INT_SETUP interrupt has been
recognized.
confirm EP0_DSET_A bit is “0”. After confirming, write data FIFO of endpoint 0.
If transmitting data is more than payload, write data after it confirming whether
EP0_DSET_A bit in DATASET register is “0”. (INT_ENDPOINT0 interrupt can be
used.) If writing all data is finished, write “0” to EP0 bit of EOP register. When
UDC receives this, the status stage finish automatically.
finishing status stage normally is recognized by external application, manage this
stage by using this interrupt signal. If status stage cannot be finished normally
and during status stage, a new SETUP token maybe received. In this case, when
INT_SETUP interrupt signal is asserted, “1” is set to STAGE_ERROR bit of
EP0_STATUS register Informing externally that the status stage cannot be
finished normally.
value showed to wLength by protocol of control read transfer type in USB. If the
application program is configured using only the wLength value, processing
cannot be carried out when the host shifts status stage without arriving at the
expected data number. At this point, shifting to status stage can be confirmed by
using INT_STATUSNAK interrupt signal. (However, releasing mask of
STATUS_NAK bit by using interrupt control register is needed.) In Vendor
Request, this problem will not occur because the receiving buffer size is set to host
controller by driver (In every host, data (data that is transmitted from device by
payload of 8 bytes) may be taken to be short packet until confirmation of payload
size on device side. Therefore, exercise care if controlling standard requests by
software.)
(a) Control Read request
When INT_SETUP is received, identify contents of request by bmRequestType,
After transmitting data prepared in application, access DATASET register, and
INT_STATUS interrupt is asserted when UDC finishes status stage normally. If
The dataphase may have finished on a data number that is shorter than the
Vendor specific
bRequest
Vendor specific
92CF26A-419
wValue
Vendor specific
wIndex
Vendor specific
wLength
(Expire 0)
TMP92CF26A
Vendor data
2009-06-25
Data