TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 520

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDMODE0
(0280H)
LCDMODE1
(0281H)
LCDSIZE
(0284H)
3.19.2
Note: When SDRAM is used as the LCDC’s display RAM, it can only be accessed by “burst 1-clock access”.
Note: <LDINV>=1 inverts all output data on the LD bus. However, the LDIV signal that indicates the inversion of
Note: Although the TMP92CF26A contains 144 Kbytes of RAM that can be used as display RAM, it may not be
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
SFRs
output data by auto bus inversion remains unchanged.
enough depending on display size and color mode.
Display RAM
00: Internal RAM
01: External SRAM
10: SDRAM
11: Reserved
Data rotation function
(Supported for 64K-color: 16bps only)
000: Normal
001: Horizontal flip 101: Reserved
010: Vertical flip
011: Horizontal & vertical flip
111: Reserved
RAMTYPE1 RAMTYPE0
Common setting
0101: 160
0110: 200
0111: 240
0000: Reserved
0001: 64
0010: 96
0011: 120
0100: 128
COM3
LDC2
7
7
0
7
0
0
LDC1
COM2
6
0
6
0
6
0
100: 90-degree
110: Reserved
LCD Size Setting Register
1000: 320
1001: 480
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
LCDMODE0 Register
LCDMODE1 Register
LD bus transfer speed
SCPW2= 0
SCPW2= 1
92CF26A-518
LDC0
COM1
SCPW1
5
0
5
0
5
1
R/W
LD bus
inversion
0: Normal
1: Invert
00: 2-clk
01: 4-clk
10: 8-clk
11: 16-clk
00: 6-clk
01: 12-clk
10: 24-clk
11: 48-clk
LDINV
COM0
4
0
SCPW0
4
0
4
1
R/W
R/W
Auto bus
inversion
0: Disable
1: Enable
(Valid only
for TFT)
Segment setting
AUTOINV
0000: Reserved
0001: 64
0010: 128
0011: 160
0100: 240
0101: 320
0110: 480
0111: 640
SEG3
0000: Reserved
0001: SR (mono)
0010: SR (4-gray)
0011: Reserved
0100: SR (16-gray)
0101: SR (64-gray)
0110: STN (256-color)
0111:STN (4096-color)
Mode selection
3
0
MODE3
3
0
3
0
Interrupt
selection
0:LLOAD
1:LVSYNC
INTMODE
SEG2
2
0
MODE2
2
0
2
0
1000: Reserved
1001: Reserved
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
LFR edge
0: LHSYNC
1:LHSYNCR
1000: STN (64K-color)
1001: Reserved
1010: TFT (256-color)
1011: TFT (4096-color)
1100: TFT (64K-color)
1101:TFT(256K-,16M-color)
1110 : Reserved
1111:
FREDGE
Front
Edge
EAR Edge
SEG1
1
0
MODE1
1
0
Reserved
1
TMP92CF26A
0
W
2009-06-25
LD bus
Trance
Speed
0: normal
1: 1/3
SCPW2
SEG0
0
0
MODE0
0
0
0
0