TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 715

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
SDCISR
SDCMM
SDRCR
SDACR
SDBLS
(5) SDRAM controller
SDRAM
access
control
register
SDRAM
Command
Interval
Setting
Register
SDRAM
refresh
control
register
SDRAM
command
register
SDRAM
HDRAM
burst length
register
Name
Address
0250H
0251H
0252H
0253H
0254H
Read
data shift
function
0: Disable
1: Enable
Always
write “0”
SRDS
R/W
7
1
−
0
TMRD
0: 1 CLK
1: 2 CLK
Always
write “0”
STMRD
6
−
0
1
92CF26A-713
TWR
0: 1 CLK
1: 2 CLK
Address multiplex
type
00: Type A (A9- )
01: Type B (A10- )
10: Type C (A11- )
11: Reserved
For
HDMA5
HDMA burst length
0:1 Word Read / Single Write
1:Full Page Read / Burst Write
SMUXW1 SMUXW0
SDBL5
STWR
R/W
5
0
1
0
TRP
0: 1 CLK
1: 2 CLK
Self
Refresh
auto
exit
function
0:Disable
1:Enable
For
HDMA4
SDBL4
STRP
SSAE
4
0
1
1
0
TRCD
0: 1 CLK
1: 2 CLK
Refresh interval
000: 47 states
001: 78 states
010: 156 states 110: 936 states
011: 312 states
Read/Write
commands
0: Without
auto pre-
charge
1: With auto
For
HDMA3
SDBL3
STRCD
precharge
SRS2
SPRE
R/W
1
0
0
3
0
TRC
000: 1 CLK
001: 2 CLK
010: 3 CLK
011: 4 CLK
Command issue
000: Don’t care
001: Initialization sequence
010: Precharge All command
100: Reserved
101: Self Refresh Entry command
110: Self Refresh Exit command
Others: Reserved
For
HDMA2
SCMM2
SDBL2
STRC2
SRS1
a. Precharge All command
b. Eight Auto Refresh commands
c. Mode Register Set command
R/W
1
0
0
0
100: 468 states
101: 624 states
2
111: 1248 states
For
HDMA1
SCMM1
STRC1
SDBL1
100: 5 CLK
101: 6 CLK
110: 7 CLK
111: 8 CLK
SRS0
R/W
1
0
0
0
0
TMP92CF26A
2009-06-25
SDRAM
controller
0: Disable
1: Enable
Auto
Refresh
0:Disable
1:Enable
For
HDMA0
SCMM0
STRC0
SDBL0
SMAC
SRC
R/W
0
0
0
0
0
0