TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 510

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

I2S0C
(180AH)
(180BH)
bit Symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Note: The transfer clock must not exceed 10 MHz. Make sure that the transfer clock is set to within 10 MHz by an
Note: It is recommended that the value to be set in I2SnC<CKn7:0> be an even number. Although it is possible to set
(3) Setting example for the clock generator (8-bit counter/6-bit counter)
appropriate combination of source clock frequency and divider value.
an odd number, the clock duty of the CK signal does not become 50%. Setting an odd number causes the High
width of the I2SnCK0 signal to become longer by one f
0, the Low width becomes longer than the High width.)
When f
follows:
and sampling frequency.
The clock generator generates the reference clock for setting the data transfer speed
•
CK07
<CLKSn>. An 8-bit counter is provided to divide the source clock by 3 to 256. (The
divider value cannot be set to 1 or 2.)
15
8-bit counter set value
I2SnCKO = f
7
0
The transfer clock is generated by dividing the clock selected by I2SnCTL
SYS
Setting the transfer clock I2SnCKO
00000000
00000001
11111111
= 60 MHz and I2SnC<CKn7:0> = 150, the data transfer speed is set as
CK06
14
6
0
= 60 [MHz]/150 = 400 [kbps]
SYS
/150
WS05
CK05
Divider value for CK signal (8-bit counter)
13
5
0
0
92CF26A-508
WS04
CK04
Divider value for WS signal (6-bit counter)
12
4
0
0
R/W
SYS
WS03
CK03
or f
11
3
0
0
Divider value
PLL
256
1
255
R/W
pulse than the Low width. (When <EDGE> =
WS02
CK02
10
2
0
0
WS01
CK01
1
9
0
0
TMP92CF26A
WS00
CK00
0
8
0
0
2009-06-25