TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 89

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.6
DMAC (DMA Controller)
can realize data transfer faster than the micro DMA function by the 900/H1 CPU.
The TMP92CF26A incorporates a DMA controller (DMAC) having six channels. This DMAC
The DMAC has the following features:
3) Various source/destination combinations
4) Transfer address mode
5) Dual-count mechanism and DMA end interrupt
6) Priorities among DMA channels (the same as the micro DMA acceptance specifications
7) DMAC bus occupancy limiting function
8) The DMAC can be used in HALT (IDLE2) mode.
1) Six independent channels of DMA
2) Two types of transfer start requests
of the INTC)
request can be selected for each channel.
from the following four types: memory to memory, memory to I/O, I/O to memory, I/O to
I/O.
request and to generate multiple DMA requests at a time. The DMA end interrupt
(INTDMA0 to INTDMA5) is also provided so that a general-purpose interrupt routine
can be used to prepare for the next processing.
than one request is asserted simultaneously or it looks as if two requests were asserted
simultaneously because one of the requests has been put on hold while other processing
was being performed, the smaller-numbered channel is given a higher priority.
excessive interference with the CPU or LCDC operation.
Hardware request (using an interrupt source connected with the INTC) or software
The combination of transfer source and destination can be selected for each channel
Only the dual address mode is supported.
Two count registers are provided to execute multiple DMA transfers by one DMA
DMA requests are basically accepted in the order in which they are asserted. If more
The DMAC incorporates a special timer for limiting its bus occupancy time to avoid
92CF26A-87
TMP92CF26A
2009-06-25