TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 354

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.15.5
Control in I
(1)
(2)
(3)
a.
SBICR1<ACK> to “1”, TMP92CF26A operates in the acknowledge mode. The
TMP92CF26A generates an additional clock pulse for an Acknowledge signal when
operating in Master Mode. In the transmitter mode during the clock pulse cycle, the
SDA pin is released in order to receive the acknowledge signal from the receiver. In
the receiver mode during the clock pulse cycle, the SDA pin is set to the Low in order
to generate the acknowledge signal.
TMP92CF26A does not generate a clock pulse for the Acknowledge signal when
operating in the Master Mode.
receiving data.
Since the <BC2:0> is cleared to 000 as a start condition, a slave address and direction
bit transmission are executed in 8 bits. Other than these, the <BC2:0> retains a
specified value.
Acknowledge Mode Specification
Number of transfer bits
Serial clock
t
t
fscl = 1/(t
When slave address is matched or detecting GENERAL CALL, and set the
Clear the <ACK> to “0” for operation in the Non-Acknowledge Mode; The
The SBICR1<BC2:0> is used to select a number of bits for next transmitting and
LOW
HIGH
outputted on the SCL pin in Master Mode. Set a communication baud rates that
meets the I
the equations shown below.
Clock source
= (2
The SBICR1 <SCK2:0> is used to select a maximum transfer frequency
=
= (2
2
C Bus Mode
LOW
n-1
n − 1
2
f
SYS
+ 29)/(f
n
+ 6)/(f
+ 36
+ t
/4
t
HIGH
HIGH
2
SYS
SYS
C bus specification, such as the shortest pulse width of t
)
/4)
/4)
Figure 3.15.8 Clock source
t
LOW
92CF26A-352
SBICR1<SCK2:0>
000
001
010
011
100
101
110
1/fscl
10
n
4
5
6
7
8
9
TMP92CF26A
LOW
2009-06-25
, based on