TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 505

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

I2S1BUF
(1810H)
A read-
modify-
write
operation
cannot be
performed Function
I2S1CTL
(1818H)
(1819H)
I2S1C
(181AH)
(181BH)
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
CPU via a 32-bit data bus. The transmission buffers I2S0BUF and I2S1BUF must be
accessed using 4-byte load instructions.
The I
0: Stop
1: Start
Source
clock
0: f
1: f
Transmission
B115
B131
15
31
2
CLKS1
SYS
PLL
TXE1
CK17
S unit is provided with the following registers. These registers are connected to the
R/W
15
15
7
7
0
0
0
B114
B130
14
30
R/W
Counter
control
0: Clear
1: Start
Figure 3.18.3 I
*CNTE1
B113
B129
13
29
CK16
14
14
6
6
0
0
I2S1 Divider Value Setting Register
B112
B128
12
28 27
B111
B127
11
WS15
CK15
I2S1 Control Register
13
13
I2S1 Buffer Register
5
5
0
Divider value for CK signal (8-bit counter)
0
2
92CF26A-503
B110
Transmission buffer register (FIFO)
B126
Transmission buffer register (FIFO)
S Channel 1 Control Registers
10
26
0: MSB
1: LSB
Stereo
/monaural
0: Stereo
1: Monaural
Transmission
start bit
B109
B125
25
9
FSEL1
WS14
CK14
DIR1
R/W
12
12
Divider value for WS signal (6-bit counter)
4
0
0
4
0
0
Undefined
Undefined
B108
B124
24
8
W
W
Bit length
0: 8 bits
1:16 bits
0: Data
1: No data
Transmission
FIFO state
B107
B123
23
7
TEMP1
WS13
CK13
BIT1
R/W
11
11
3
R
3
0
1
0
0
B106
B122
22
6
R/W
Output format
00: I
01: Left
WS level
0: Low left
1: High left
B105
B121
21
DTFMT11
5
WLVL1
WS12
CK12
R/W
2
10
10
S
2
2
0
0
0
0
B104
B120
20
4
10: Right
11:Reserved
B103
B119
Data output
clock edge
0: Falling
1: Rising
19
3
DTFMT10
EDGE1
WS11
CK11
R/W
1
9
1
9
0
0
0
0
B102
B118
18
2
B101
B117
17
System
clock
0: Disable
1: Enable
Clock
operation
(after
transmis-
sion)
0: Enable
1: Disable
TMP92CF26A
1
SYSCKE1
CLKE1
WS10
CK10
2009-06-25
0
B100
B116
0
8
0
0
8
0
0
16
0