TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 710

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
B0CSH
B1CSH
B2CSH
B0CSL
B1CSL
B2CSL
(3) Memory controller (1/4)
BLOCK0
CS/WAIT
control
register
low
BLOCK0
CS/WAIT
control
register
high
BLOCK1
CS/WAIT
control
register
low
BLOCK1
CS/WAIT
control
register
high
BLOCK2
CS/WAIT
control
register
low
BLOCK2
CS/WAIT
control
register
high
Name
Address
0140H
0141H
0144H
0145H
0148H
0149H
Write waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0011: 6 states +
Others: Reserved
Write waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0011: 6 states +
Others: Reserved
Write waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0011: 6 states +
Others: Reserved
CS select
0: Disable
1: Enable
CS select
0: Disable
1: Enable
CS select
0: Disable
1: Enable
B0WW3
B1WW3
B2WW3
R/W
R/W
B0E
B1E
B2E
7
0
0
0
0
0
1
R/W
0: 16 MB
1: Sets
B0WW2
B1WW2
B2WW2
WAIT
WAIT
WAIT
B2M
6
0
0
0
0
0010: 1 wait
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
area
0010: 1 wait
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
0010: 1 wait
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
92CF26A-708
pin input mode
pin input mode
pin input mode
B1WW1
B2WW1
B0WW1
5
1
1
1
Dummy
cycle
0:No insert
1: Insert
Dummy
cycle
0:No
1: Insert
Dummy
cycle
0:No
1: Insert
B1WW0
B2WW0
B0WW0
B0REC
B1REC
B2REC
insert
insert
0
4
0
0
0
0
0
R/W
R/W
R/W
Read waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0011: 6 states +
Others: Reserved
Read waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0011: 6 states +
Others: Reserved
Read waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0011: 6 states +
Others: Reserved
00: ROM/SRAM
01: Reserved
10: Reserved
11: Reserved
00: ROM/SRAM
01: Reserved
10: Reserved
11: SDRAM
00: ROM/SRAM
01: Reserved
10: Reserved
11: SDRAM
B0WR3
B1WR3
B2WR3
B0OM1
B1OM1
B2OM1
3
0
0
0
0
0
0
B0WR2
B1WR2
B2WR2
B0OM0
B1OM0
B2OM0
R/W
WAIT
WAIT
R/W
WAIT
R/W
2
0
0010: 1 wait
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
0
0
0010: 1 wait
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
0
0
0
0010: 1 wait
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
pin input mode
pin input mode
pin input mode
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
B0BUS1
B1BUS1
B2BUS1
B0WR1
B1WR1
B2WR1
TMP92CF26A
1
1
0
1
0
1
0
2009-06-25
B0BUS0
B1BUS0
B2BUS0
B0WR0
B1WR0
B2WR0
0
0
0
0
0
0
1