TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 285

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
A read-
modify-write
operation
cannot be
performed
TA3FFCR
(110DH)
Bit symbol
Read/Write
Reset State
Function
Note: The values of bits 4 to 6 of TA3FFCR are “1” when read.
Inversion signal for timer flip-flop 3 (TA3FF)
(Don’t care except in 8-bit timer mode)
Inversion of TA3FF
Control of TA3FF
<TA3FFC1:0>
7
TA3FFIS
TA3FFIE
6
TMRA3 Flip-Flop Control Register
Figure 3.12.13 Register for TMRA
00
01
10
11
5
0
1
0
1
92CF26A-283
Inversion by TMRA2
Inversion by TMRA3
Disabled
Enabled
Inverts the value of TA3FF (Software inversion)
Sets TA3FF to “1”
Clears TA3FF to “0”
Don’t care
4
00: Invert TA3FF
01: Set TA3FF
10: Clear TA3FF
11: Don’t care
TA3FFC1
3
1
R/W
TA3FFC0
2
1
TA3FF
control for
inversion
0: Disable
1: Enable
TA3FFIE
1
0
R/W
TA3FF
inversion
select
0: TMRA2
1: TMRA3
TA3FFIS
TMP92CF26A
0
0
2009-06-25

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