TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 392

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

DATASET2
(07CDH)
DATASET1
(07CCH)
3.16.3.12 DATASET Register
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
Note: DATASET1<EP3_DSET_B>, DATASET2 registers are not used in the TMP92CF26A.
•
data or not.
the bit which corresponds to the corresponding endpoint is set to “1” and an interrupt
generated. And, when the application reads the 1-packet data, this bit is cleared to “0”.
In transmit status, when it has completed the 1-packet data transfer to FIFO, this bit
is set to “1”. And when valid data is transferred to the USB host, this bit is cleared to
“0” and an interrupt generated.
•
data to be read. Access EPx_SIZE register, determine the size of the data that should
be read, and read data of this size. When this bit is “0”, there is no data to be read.
transfer data under the FIFO payload. If this bit is “1”, because FIFO has transfer
data waiting, transfer data to FIFO from UDC after the corresponding bit has been
cleared to “0”. When a short-packet is transferred, access EOP register after writing
transmission data to the corresponding endpoint.
mode.
access the current frame. In this case, whether bit A or B is set to “1”, it is renewed
according to the shifting frame.
Dual packet mode
(DATASET1: Bit3, bit5 and bit7
This register shows whether FIFO contains data or not.
The application program can access this register to check whether FIFO contains
In the receiving status, when valid data transfer from the USB host has finished,
EP3_DSET_B EP3_DSET_A EP2_DSET_B EP2_DSET_A EP1_DSET_B EP1_DSET_A
EP7_DSET_B EP7_DSET_A EP6_DSET_B EP6_DSET_A EP5_DSET_B EP5_DSET_A EP4_DSET_B EP4_DSET_A
These bits show whether FIFO of the corresponding endpoint has data or not.
In receive mode endpoint, if the corresponding endpoint bit is “1”, FIFO contains
In transmit mode endpoint, if the corresponding endpoint bit is “0”, the CPU can
These bits become effective in the dual packet mode. FIFO has 2-packets in this
Each packet (packet-A and packet-B) has its own DATASET-bit.
Unlike as in the case above, in isochronous transfer, this shows the packet that can
Single packet mode
(DATASET1: Bit0, bit2, bit4 and bit6
7
R
7
R
0
0
6
R
6
R
0
0
92CF26A-390
5
R
5
R
0
0
DATASET2: Bit1, bit3 bit5 and bit7)
4
R
4
R
0
0
DATASET2: Bit0, bit2, bit4 and bit6)
R
3
R
3
0
0
2
R
2
R
0
0
TMP92CF26A
1
R
1
0
2009-06-25
EP0_DSET_A
R
R
0
0
0
0