TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 192

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

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(5) Recovery cycle (data hold time) control
BnCSH<BnREC>
When no dummy cycle is inserted (0 wait state)
When a single dummy cycle is inserted (0 wait state)
read cycle is defined by the AC specification. This may lead to data conflicts. Thus, to
avoid this problem, a single dummy cycle can be inserted immediately after an access
cycle for the CSm space by setting the BmCSH<BmREC> bit to 1.
cycle.
For some memory, the data hold time after when the
This single dummy cycle is inserted when another CS space is accessed in the next bus
0
1
A23 to A0
A23 to A0
SDCLK
SDCLK
CSm
CSn
RD
CSm
CSn
RD
92CF26A-190
Dummy
No dummy cycle is inserted (Default).
Dummy cycle is inserted.
CE
or
OE
signal is asserted in a
TMP92CF26A
2009-06-25