TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 228
TMP92xy26AXBG
Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet
1.TMP92XY26AXBG.pdf
(768 pages)
Specifications of TMP92xy26AXBG
Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
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SDLUDQM
SDLUDQM
SDLLDQM
SDLLDQM
SDRAS
SDCAS
SDRAS
SDCAS
SDCKE
SDCKE
A15-A0
D15-D0
A15-A0
D15-D0
SDCLK
SDWE
SDCLK
SDCS
SDWE
SDCS
A10
A10
Active
Active
Bank
Bank
RA
RA
RA
RA
t
t
1CLK
1CLK
RCD
RCD
=
=
Figure 3.10.3 Full-Page Read Cycle Timing
Read
Read
4CLK
Figure 3.10.2 1-Word Read Cycle Timing
4CLK
CA (n)
CAS Latency=2CLK
CAS Latency=2CLK
CA (n)
D (n)
D (n)
92CF26A-226
D (n+2)
1CLK
Read
CA (n+2)
CAS Latency=2CLK
3CLK
D (n+4)
1CLK
D (n+2)
Burst Stop Cycle 2CLK
D(dmy)
Burst Stop
Read
CAS Latency=2CLK
3CLK
CA (n+4)
D (dmy)
A15-0
A10
D (n+4)
TMP92CF26A
2009-06-25
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