TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 353

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SBIBR0
(1244H)
A read-
modify-write
operation
cannot be
performed
SBIDBR
(1241H)
A read-
modify-write
operation
cannot be
performed
I2CAR
(1242H)
modify-write
operation
cannot be
performed
A read-
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Bit symbol
Read/Write
Reset State
Function
Note1: When writing transmitted data, start from the MSB (bit 7).Receiving data is placed from LSB(bit0).
Note2: SBIDBR can’t be read the written data because of it has buffer for writing and buffer for reading
individually.Therefore Read modify write instruction (e.g.“BIT” instruction ) is prohibitted.
Always
read “0”
SA6
W
7
0
7
−
0
DB7
7
Figure 3.15.7 Registers for the I
Slave address selection for when device is operating as slave device
Serial Bus Interface Baud Rate Register 0
IDLE2
0: Stop
1: Run
Serial Bus Interface Data Buffer Register
SA5
I2SBI
R/W
6
0
6
0
DB6
6
I
2
C Bus Address Register
92CF26A-351
SA4
5
0
5
−
1
DB5
5
R (received)/W (transfer)
SA3
4
0
4
1
−
DB4
4
Undefined
Always read as “1”
R/W
2
C bus mode
SA2
3
0
R
3
Address recognition mode specification
1
0
1
−
DB3
3
Operation during IDLE 2 mode
0
1
Slave address recognition
Non slave address recognition
Stop
Operation
SA1
2
0
2
−
1
DB2
2
SA0
1
0
1
1
−
DB1
TMP92CF26A
1
2009-06-25
Address
recognition
mode
specification
Always
write “0”.
ALS
R/W
0
0
0
0
−
DB0
0