TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 430

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(b) Interrupt transfer type
(b-1) Interrupt transmitting mode (Toggle mode)
(b-2) Interrupt transmission mode (Not toggle mode)
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transfer.
same as for transmission bulk transfer. Interrupt transfer can be transferred without
using toggle bit. In this case, if ACK handshake from host is not received, toggle bit is
renewed, and finish is normal. The UDC clears FIFO for next transfer.
from host is not received, transaction is different.
Interrupt transfer type uses the same transaction format as transmission bulk
For transmission using toggle bit, hardware setting and answer in the UDC are the
UDC operation is same as in bulk transmission mode. Please refer to section (a).
This is basically the same as bulk transmission mode. However, if ACK handshake
When ACK handshake from host is received after transmission of data packet
UDC finishes normally by above transaction. FIFO can receive next data.
If a time out occurs without receiving ACK from host,
Execute above setting. This setting is the same except for STATUS changes.
Clear FIFO.
Clear DATASET register.
Renew toggle bit and prepare for next.
Set STATUS to READY.
Clear FIFO.
Clear DATASET register.
Renew toggle bit and prepare for next.
Set STATUS to TX_ERR.
92CF26A-428
TMP92CF26A
2009-06-25