TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 206
TMP92xy26AXBG
Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet
1.TMP92XY26AXBG.pdf
(768 pages)
Specifications of TMP92xy26AXBG
Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
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FFFFFFH
FFFF00H
Address memory map
C00000H
000000H
200000H
400000H
600000H
800000H
Figure 3.9.1 Recommended Memory Map for the Maximum Expansion (Logical address)
Note1: CSZA is a chip-select signal for not only bank 0 through bank 127 of the LOCAL-Z area, but also for the
Note2: In case of connecting SDRAM to the Y-area, the maximum expanded memory size is 64 MB (2 MB × 32).
On-chip I/O, RAM
COMMON-Z
COMMON-X
COMMON-Y
Vector area
LOCAL-Z
LOCAL-X
LOCAL-Y
(4 MB)
(4 MB)
(2 MB)
(2 MB)
(2 MB)
(2 MB)
COMMON-Z area.
Bank 0
Bank 0
Bank 0
SDCS
:
:
512 MB (4 MB × 128)
On-chip memory area
Memory area overlapping with COMMON-area, which cannot be configured as LOCAL-area.
CSZA
1
1
1
: 64 MB (when connecting SDRAM: 2MB×32) (Note 2)
2
2
2
pin (Note 1)
512 MB (2 MB × 256)
92CF26A-204
3
3
3
or
CSXA
・・・ 15
・・・ 15
・・・ 127 128 ・・・ 255 ・・・ 384 ・・・ 511
ND
CS
ND
0
1
1
CE
CE
pin: 128MB (2MB×64)
pin
pin (512 MB)
pin (512 MB)
・・・
CSZB
・・・
pin
63
255 256 ・・
・・・
512 MB (2 MB × 256)
CSXB
CSZD
pin
511
pin
Memory controller
TMP92CF26A
CS3-space
CS1-space
setting
CS2-space
2009-06-25
4 MB
4 MB
8 MB
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