TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 103

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note 1: When SDRAM is used, the overhead time is added as shown below.
Note 2: When internal RAM is used, the overhead time is added as shown below.
(2) CPU + LDMA
t
STOP
the CPU and getting a bus acknowledgement.
Therefore, LDMA must have higher priority than the CPU. While LDMA is being
performed, the CPU cannot execute instructions.
what degree LDMA would interfere with the CPU operation based on the display RAM
type, display RAM bus width, LCDD type, display pixel count, and display quality.
line is defined as “t
mode.
taken up by t
The LCD controller performs DMA transfer (LDMA) after issuing a bus request to
If LDMA is not performed properly, the LCD display function cannot work properly.
To display data on the LCD using the LCD controller, it is necessary to estimate to
The time the CPU stops operation while the LCD controller transfers data for one
16-bit external SRAM
Internal RAM
16-bit external SDRAM : t
SegNum
K
The CPU bus stop rate indicates what proportion of the 1-line data update time t
CPU bus stop rate = t
(LDMA) = (SegNum × K / 8) × t
t
t
STOP
STOP
Monochrome
4 gray scales
16 gray scales
256 colors
4096 colors
65536 colors
262144/16777216 colors
[s] = (SegNum × K/8) × t
[s] = ( SegNum × K/8 )× t
STOP
(LDMA) and is calculated as follows:
STOP
STOP
(LDMA)”, which is calculated as shown below for each display
92CF26A-101
: t
: t
: Number of bits needed for displaying 1 pixel
K = 12
LRD
LRD
(LDMA) [s] / LHSYNC [period: s]
LRD
LRD
LRD
+ ((1/f
+ (1/f
= 1 / f
= (2 + wait count) / f
= 1 / f
LRD
SYS
SYS
: Number of segments to be displayed
K = 1
K = 2
K = 4
K = 8
K = 16
K = 24
) × 8)
)
SYS
SYS
[Hz] / 2
[Hz] / 4
SYS
[Hz] / 2
TMP92CF26A
2009-06-25
LP
is