TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 541

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDHWB8
(0299H)
LCDHSW
(0294H)
Signal Name
LCP0
LHSYNC signal
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
specified in a range of 1 to 512 pulses of the LCP0 clock.
LCP0 clock.
The enable width of the LHSYNC signal is set using LCDHSW<HSW8:0>. It can be
The enable width is represented by the following equation:
Enable width = <HSW8:0> + 1
Thus, when LCDHSW<HSW8:0> is set to “0”, the enable width is set as one pulse of the
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)
HSW7
O2W9
7
0
7
0
HSW6
O2W8
6
0
6
0
Signal width Bit8,9 Register
LHSYNC width Register
92CF26A-539
LCP0 clock = 1, 2, 3 … 512 pulses
HSW5
O1W9
5
5
0
0
High width setting
LHSYNC width (bits 7-0)
HSW4
O1W8
4
0
4
0
W
W
width (bit 8)
LGOE0
HSW3
O0W8
3
0
3
0
LLOAD width (bits 9-8)
HSW2
LDW9
2
0
2
0
HSW1
LDW8
1
0
1
0
TMP92CF26A
width (bit 8)
2009-06-25
LHSYNC
HSW0
HSW8
0
0
0
0