TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 168

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PUDR
(009CH)
PU
(00A4H)
PUCR
(00A6H)
PUFC
(00A7H)
Bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note: When PU is used as LD23 to LD16, set applicable PUnC to “1”.
Note1: A read-modify-write operation cannot be performed for the registers PUCR, PUFC.
Note2: When use PU as LD23 to LD16, set PUnC to “1”. When use PU5 as LD21, set PU5C to “1”.
0: Port
1: LD23
PU7C
PU7D
PU7F
PU7
7
7
7
7
1
−
0
−
0
−
0: Port
1: LD22
PU6D
PU6C
PU6F
PU6
Figure 3.7.56 Register for Port U
6
6
6
6
1
−
0
−
0
−
Data from external port (Output latch register is cleared to “0”)
Input/Output buffer drive register for standby mode
0: Port
1: LD21@
<PU5C>=1
Port U function register
Port U control register
PU5C
PU5F
PU5D
PU5
Port U drive register
5
5
5
5
0
−
0
−
1
−
92CF26A-166
Port U register
0: Port
1: LD20
PU4C
PU4D
PU4F
0: Input 1: Output
PU4
4
4
0
−
4
4
0
−
1
−
R/W
R/W
W
W
−
0: Port
1: LD19
PU3C
PU3D
PU3F
PU3
3
3
3
3
0
−
0
−
1
−
0: Port
1: LD18
PU2C
PU2D
PU2F
PU2
2
2
2
0
−
2
1
−
0
−
0: Port
1: LD17
PU1C
PU1D
PU1F
PU1
1
1
1
1
0
−
1
−
0
−
0: Port
1: LD16
TMP92CF26A
PU0C
PU0D
PU0F
PU0
0
0
0
0
0
−
1
−
0
−
2009-06-25