TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 257

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

NDECCRD4
(08CCH)
(08CDH)
Note: Before reading ECC from the NAND Flash ECC register, be sure to set NDFMCR0<ECCE> to “0”. The ECC in
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
NDFMCR0<ECCE> to “0” causes the corresponding ECC to be set in this register. (The
ECC in this register is updated when NDFMCR0<ECCE> changes from “1” to “0”.)
data. In the case of Reed-Solomon codes, 80 bits of ECC are generated for up to 518 bytes of
valid data. A total of 80 bits of registers are provided, arranged as five 16-bit registers.
These registers must be read in 16-bit units and cannot be accessed in 32-bit units.
parity for the first 256 bytes is stored in the NDECCRD0 register, the 6-bit column parity
for the first 256 bytes in the NDECCRD1 register (<ECCE7:2>), the 16-bit line parity for
the second 256 bytes in the NDECCRD2 register, and the 6-bit column parity for the second
256 bytes in the NDECCRD3 register (<ECCD7:2>). In this case, the NDECCRD4 register
is not used.
NDECCRD1, NDECCRD2, NDECCRD3 and NDECCRD4 registers.
The NAND Flash ECC register is used to read ECC generated by the ECC generator.
After valid data has been written to or read from the NAND Flash, setting
When Hamming codes are used, 22 bits of ECC are generated for up to 256 bytes of valid
After ECC calculation has completed, in the case of Hamming codes, the 16-bit line
In the case of Reed-Solomon codes, 80 bits of ECC are stored in the NDECCRD0,
NDECCRD0
NDECCRD1
NDECCRD2
NDECCRD3
NDECCRD4
the NAND Flash ECC register is updated when NDFMCR0<ECCE> changes from “1” to “0”. Also note that
when the ECC in the ECC generator is reset by NDFMCR0<ECCRST>, the contents of this register are not
reset.
Register
Name
ECCD15
ECCD7
15
7
0
0
Figure3.11.7 NAND Flash ECC Registers
ECCD14
ECCD6
(for the second 256 bytes)
(for the second 256 bytes)
14
6
0
0
NAND Flash ECC Register 4
(for the first 256 bytes)
(for the first 256 bytes)
[7:2] Column parity
[7:2] Column parity
[15:0] Line parity
[15:0] Line parity
Hamming
Not in use
ECCD13
92CF26A-255
ECCD5
13
5
0
0
NAND Flash ECC Register (15-8)
NAND Flash ECC Register (7-0)
ECCD12
ECCD4
12
4
0
0
R
R
ECCD11
ECCD3
11
3
0
0
Reed-Solomon ECC code 79:64
Reed-Solomon ECC code 63:48
Reed-Solomon ECC code 47:32
Reed-Solomon ECC code 31:16
Reed-Solomon ECC code 15:0
Reed-Solomon
ECCD10
ECCD2
10
2
0
0
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
ECCD1
ECCD9
1
9
0
0
TMP92CF26A
2009-06-25
ECCD0
ECCD8
0
0
8
0