TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 239
TMP92xy26AXBG
Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet
1.TMP92XY26AXBG.pdf
(768 pages)
Specifications of TMP92xy26AXBG
Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
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3.10.3
as the transfer source.
•
The following shows an example of calculating the HDMA transfer time when SDRAM is used
An Example of Calculating HDMA Transfer Time
Transfer from SDRAM to internal SRAM
Conditions:
System clock (f
SDRAM read cycle
16-bit data bus
SDRAM Auto Refresh interval: 936 states (15.6 μs)
Internal RAM write cycle
Number of bytes to transfer
Calculation example:
(a) Read/write time
(b) Burst start/stop time
(c) Auto Refresh time
Transfer time = (SDRAM read time + SRAM write time) × transfer count
Total transfer time = (a) + (b) + (c)
is assumed that Auto Refresh occurs once here.
(SDRAM read 1 state × 2 + Internal RAM write 1 state) × 512 bytes/4 bytes
= 384 states × 1/60 MHz
= 6.4 μs
Start (TRCD: 2CLK) 5 states + Stop 2 states
= 7states/60 MHz
= 0.117 μs
Based on the above (a), Auto Refresh occurs once or zero times in 384 states. It
= 7 states × 1/60 MHz
= 0.117 μs
(Precharge (TRP: 2CLK) 2 states + AREF (TRC: 5CLK) 5 states) ×AREF once
SYS
)
+ (Precharge time + Auto Refresh time) × Auto Refresh count
+ (SDRAM burst start + stop time)
= 6.4 μs + 0.117 μs + 0.117 μs
= 6.634 μs
92CF26A-237
: 60 MHz
: Full page (5-1-1-1), 16-bit data bus
: 1 state, 32-bit data bus
: 512 bytes
TMP92CF26A
2009-06-25
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