TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 277

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: If a value smaller than the up-counter value is written to the timer register while the timer is counting up, this will
Note: If an inversion by the match-detect signal and a setting change via the TMRA1 flip-flopcontrol register occur
cause the timer to overflow and an interrupt cannot be generated at the expected time. (The value in the timer
register canbe changed without any problem if the new value is larger than the up-counter value.) In 16-bit
interval timer mode, be sure to write to both TA0REG and TA1REG in this order (16 bits in total), The compare
circuit will not function if only the lower 8 bits are set.
simultaneously, the resultant operation varies depending on the situation, as shown below.
obtained.
(4)
(5)
8-bit interval timer mode
16-bit interval timer mode
80bit PWM mode
8-bit PPG mode
•
•
•
Be sure to stop the timer before changing the flip-flop incersion setting.
If the setting is chaged while the timer is counting, proper operation cannot be
flip-flop will be inverted only once.
simultaneously, the timer flip-flop will be set to 1.
simultaneously the flip-flop will be cleared to 1.
timer register. If they match, the up counter is cleared to “0” and an interrupt
signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the
timer flip-flop is inverted at the same time.
(8-bit comparator output) of each interval timer.
TA1FFCR<TA1FFIE> in the timer flip-flops control register. A reset clears the
value of TA1FF to “0”. Writing “01” or “10” to TA1FFCR<TA1FFC1:0> sets TA1FF
to “0” or “1”. Writing “00” to these bits inverts the value of TA1FF. (This is known
as software inversion.)
timer output, the timer flip-flop should be set beforehand using the port function
registers.
If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the
If an inversion by the match-detect signal and an attempt to set the flip-flop to 1 via the register occur
If an inversion by the match-detect signal and an attempt to clear the flip-flop to 0 via the register occur
Comparator (CP0, CP1)
The comparator compares the value in an up counter with the value set in a
Timer flip-flop (TA1FF)
The timer flip-flop (TA1FF) is a flip-flop inverted by the match detect signals
Whether inversion is enabled or disabled is determined by the setting of the bit
The TA1FF signal is output via the TA1OUT pin. When this pin is used as the
The condition for TA1FF inversion varies with mode as shown below
92CF26A-275
: UC0 matches TA0REG or UC1 matches TA1REG
(Select either one of the two)
: UC0 matches TA0REG or UC1 matches TA1REG
: UC0 matches TA0REG or a 2
: UC0 matches TA0REG or UC0 matches TA1REG
n
overflow occurs
TMP92CF26A
2009-06-25