TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 230

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(2) Execution of instructions on SDRAM
(3) Command interval adjustment function
COMMAND
COMMAND
COMMAND
operations cannot be performed.
internal RAM.
SDRAM to be accessed at optimum cycles even if the operation frequency is changed by clock
gear.
frequency of the TMP92CF26A and the AC specifications of the SDRAM.
SDCKE
SDCLK
SDCLK
SDCLK
The CPU can execute instructions that are stored in the SDRAM. However, the following
These operations, if needed, must be executed by branching to other memory such as
Command execution intervals can be adjusted for each command. This function enables the
Command intervals should be set in the SDCISR register according to the operating
The SDCICR register must not be changed while the SDRAM is being accessed.
The timing waveforms for various cases are shown below.
(c) Self Refresh Exit
(a) Mode Register Set command
(b) Auto Refresh command
a) Executing the HALT instruction
b) Changing the clock gear setting
c) Changing the settings in the SDACR, SDCMM, and SDCISR registers
NOP
NOP
XXX
REFRESH
MRS
AUTO
NOP
Exit Self Refresh
*TMRD=2CLK (SDCISR<STMRD>= “1”)
92CF26A-228
*TRC=5CLK (SDCISR<STRC2:0>= “100”)
*TRC=5CLK (SDCISR<STRC2:0>= “100”)
NOP
NOP
NOP
TMRD
Command
NOP
NOP
Next
TRC
TRC
NOP
NOP
NOP
NOP
NOP
TMP92CF26A
Command
Command
2009-06-25
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