TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 654

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCD DMA operation 1
LCD DMA operation 2
HDMA operation
LHSYNC
(Worst case)
LD-bus
LCP0
Figure 3.27.1 Example of Data Bus Occupancy Timing in Non-Debug Mode
depicting the LHSYNC signal, LCP0 signal, and LD-bus signal for transferring data
from the LCD controller to the LCD driver, and the LCD DMA operation timing for
reading data from the display RAM.
operation 1) is started, this operation must wait until HDMA is finished before it can
be performed (LCD DMA operation 2).
operation is finished before the next LCD driver output is started.
5) Data bus occupancy
Figure 3.27.1 shows an example of data bus occupancy timing in non-debug mode,
If HDMA is asserted immediately before the DMA operation for the LCD (LCD DMA
Taking the above into account, it is necessary to ensure that each LCD DMA
and DMAC) that function as bus masters apart from the CPU. Therefore, it is
necessary to estimate the bus occupancy time of each bus master and control each
function accordingly to ensure proper operation of each function. (For details,
please refer to the chapter on the DMA controller.)
program that runs in the background must also be taken into account in
programming. When the program stops at a breakpoint (including step execution),
the CPU operation is halted but the LCD controller, SDRAM controller and DMA
controller remain active. At this time, the steal program also runs in the
background. Once the steal program obtains the bus, it occupies the bus for 80
times of debug transmission clock (LH_SYNCLK) maximum. Therefore, in some
cases, other DMA operations (LCD display, DMAC data transfer, SDRAM refresh)
may not be performed at desired timing.
The TMP92CF26A includes three controllers (LCD controller, SDRAM controller
In debug mode, in addition to the operations of these bus masters, a steal
92CF26A-652
2
1
Setup time 1
TMP92CF26A
2009-06-25
Setup time 2