TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 336

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SCLK0 output
(<SCLKS> = 0:
rising edge mode)
SCLK0 output
(<SCLKS> = 1:
falling edge mode)
TXD0
ITX0C
(INTTX0 interrupt
request)
Timing of transmited
data writing
Figure 3.14.13 Transmitting Operation in I/O Interface Mode (SCLK0 Output Mode)
SCLK0 input
(<SCLKS> = 0:
rising edge mode)
SCLK0 input
(<SCLKS> = 1:
falling edge mode)
TXD0
ITX0C
(INTTX0 intterrupt
reqest)
a.
Figure 3.14.14 Transmitting Operation in I/O Interface Mode (SCLK0 Input Mode)
Transmission
and SCLK0 pins respectively each time the CPU writes the data to the Transmission
Buffer. When all data is output, INTES0 <ITX0C> will be set to generate the INTTX0
interrupt.
becomes active after the data has been written to the Transmission Buffer by the CPU.
In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0
In SCLK Input Mode, 8-bit data is output on the TXD0 pin when the SCLK0 input
When all data is output, INTES0 <ITX0C> will be set to generate INTTX0 interrupt.
Bit0
92CF26A-334
Bit0
Bit1
Bit1
Bit5
Bit6
Bit6
Bit7
Bit7
TMP92CF26A
2009-06-25
(Internal clock
timing)