TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 394

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

EP0_STATUS
(0790H)
EP1_STATUS
(0791H)
EP2_STATUS
(0792H)
EP3_STATUS
(0793H)
EP4_STATUS
(0794H)
EP5_STATUS
(0795H)
EP6_STATUS
(0796H)
EP7_STATUS
(0797H)
TOGGLE Bit (Bit6)
SUSPEND (Bit5)
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
3.16.3.13 EPx_STATUS Register (x: 0 to 7)
0: TOGGLE
1: TOGGLE
0: RESUME
1: SUSPEND
Note: EP4, 5, 6 and 7_STATUS registers are not used in the TMP92CF26A.
to all endpoints.
These registers are status registers for each endpoint. The <SUSPEND> is common
7
7
7
7
7
7
7
7
Bit0
Bit1
TOGGLE
TOGGLE
TOGGLE
TOGGLE
TOGGLE
TOGGLE
TOGGLE
TOGGLE
6
R
6
R
6
R
6
R
6
R
6
R
6
R
6
R
0
0
0
0
0
0
0
0
SUSPEND
SUSPEND
SUSPEND
SUSPEND
SUSPEND
SUSPEND
SUSPEND
SUSPEND
5
R
5
R
5
R
5
R
5
R
5
R
5
R
5
R
0
0
0
0
0
0
0
0
92CF26A-392
This bit shows status of toggle sequence bit.
This bit shows status of UDC power management.
In the SUSPEND status, access to UDC is limited.
For details, refer to 3.16.9.
STATUS[2]
STATUS[2]
STATUS[2]
STATUS[2]
STATUS[2]
STATUS[2]
STATUS[2]
STATUS[2]
4
R
4
R
4
R
4
R
4
R
4
R
4
R
4
R
1
1
1
1
1
1
1
1
STATUS[1]
STATUS[1]
STATUS[1]
STATUS[1]
STATUS[1]
STATUS[1]
STATUS[1]
STATUS[1]
3
R
3
R
3
R
3
R
3
R
3
R
3
R
3
R
1
1
1
1
1
1
1
1
STATUS[0]
STATUS[0]
STATUS[0]
STATUS[0]
STATUS[0]
STATUS[0]
STATUS[0]
STATUS[0]
2
R
2
R
2
R
2
R
2
R
2
R
2
R
2
R
1
1
1
1
1
1
1
1
FIFO_DISABLE STAGE_ERR
FIFO_DISABLE STAGE_ERR
FIFO_DISABLE STAGE_ERR
FIFO_DISABLE STAGE_ERR
FIFO_DISABLE STAGE_ERR
FIFO_DISABLE STAGE_ERR
FIFO_DISABLE STAGE_ERR
FIFO_DISABLE STAGE_ERR
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
0
0
0
0
0
0
0
0
TMP92CF26A
2009-06-25
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
0
0
0
0
0
0