TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 638

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

BROMCR
(016CH)
Interrupt Source
Bit Symbol
Read/Write
Reset State
Function
• Exiting the Power Cut Mode
Note 1: The signals that are serviced as interrupt signals in normal mode can be used as Wake-up signals to exit the
Note 2: Once the PMCCTL<PCM_ON> bit is set to 1, it remains in this state. To re-enter the Power Cut ｍode, it is
Note 3: Please not that some settings must be configured by software,for the Power Cut mode is exited using the boot
reset. (It is prohibited to exit the reset state when DVCC1A is off. A reset signal must be
asserted after supplying power to DVCC1A and waiting for its voltage to fully stabilize.)
The interrupts that can be used to exit the Power Cut mode are the RTC interrupt, INT0 to
INT7 (TSI interrupts) and INTKEY interrupts.
from 0 to 1 allowing for the power to be supplied to each block, from which power has been
removed. After the warm-up time specified by the PMCCTL<WUTM1:WUTM0> bits has
elapsed, HOT_RESET is automatically negated and the CPU boots from the on-chip boot
ROM regardless of the external AM pin state. All external ports retain the state of before
entering the Power Cut mode except for the PnDR pin, which is also negated upon negation
of HOT_RESET.
program. If this bit is set to 1, a program execution jumps to address 46000H in the on-chip
RAM before initializing any registers. The <PCM_ON> bit in the PMC is cleared to “0” by
software. At the same time, ensure that the warm-up time is reset to the initial value. (The
PMCCTL<WUTM1:0> bits must be written as 00h.)
External
* Output pin: Hi-Z state
* Input gates of input pins: OFF → ON
RTC
Key
The Power Cut mode can be exited by the assertion of external interrupt or the internal
When an interrupt request is accepted, the power management signal (PWE) changes
The PMCCTL <PCM_ON> bit in the PMC is first checked in the on-chip boot-ROM
Power Cut Mode.
necessary to clear this bit to 0 once and then set it to 1 again. At this time, it is required to wait for at least 31 μs
after clearing the PCM_ON bit to 0.
ROM.
Table 3.25.1 Interrupts Used for Waking Up from the PCM
7
Symbol
INTRTC
INTKEY
6
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
92CF26A-636
5
Only configurable as rising-edge triggered
Only configurable as rising-edge triggered
When used as TSI, the debounce circuit should be disabled.
Only configurable as rising-edge triggered
KI0 to KI8
Only configurable as rising-edge triggered
Only configurable as rising-edge triggered
Only configurable as rising-edge triggered
Only configurable as rising-edge triggered
Only configurable as rising-edge triggered
Only configurable as falling-edge triggered
→ Set to 1 or 0
4
3
Remarks
NAND Flash
Area CS
Output
0: Enable
1: Disable
CSDIS
2
1
Boot-ROM
0: Use
1: Bypass
ROMLESS
R/W
1
0
TMP92CF26A
2009-06-25
Vector
Address
Translation
0: Disable
1: Enable
VACE
0
1