TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 331

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
SC0MOD0
(1202H)
3.14.3
Bit symbol
Read/Write
Reset State
Function
SFR
Figure 3.14.6 Serial Mode Control Register (channel 0, SC0MOD0)
Transfer
data bit 8
TB8
7
0
Hand shake
0: CTS
1: CTS
disable
enable
CTSE
6
0
Receive
function
0: Receive
1: Receive
disable
enable
RXE
92CF26A-329
5
0
Wake up
function
0: disable
1: enable
WU
4
0
R/W
Serial Transmission
Mode
00: I/O interface Mode
01: 7-bit UART Mode
10: 8-bit UART Mode
11: 9-bit UART Mode
SM1
3
0
Serial transmission clock source (UART)
Serial Transmission Mode
Wake-up function
Receiving Function
Handshake function (/CTS pin)
Transmission data bit 8
Note: The clock selection for the I/O
00 TMRA0 match detect signal
01 Baud rate generator
10 Internal clock f
11 External clock (SCLK0 input)
00
01
10
11
0
1
0
1
0
1
9-Bit UART
Interrupt generated
whenever data is received
Interrupt generated only
when RB8 = 1
Receive disabled
Receive enabled
Disabled (always transferable)
Enabled
I/O Interface Mode
UART mode
interface mode is controlled by the
serial bontrol register (SC0CR).
SM0
2
0
Serial transmission clock
(UART)
00: TMRA0 trigger
01: Baud rate generator
10: Internal clock f
11: External clock
(SCLK0 input)
SC1
IO
1
0
7-bit mode
8-bit mode
9-bit mode
TMP92CF26A
Other Modes
2009-06-25
SC0
Don’t care
0
0
IO

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