TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 362

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SCL
SDA
<PIN>
INTSBI
interrupt request
Figure 3.15.15 Example in which <BC2:0> = “000” and <ACK> = “1” in transmitter mode
(3) 1-word Data Transfer
Output from master
Output from slave
completed, and determine whether the mode is a master or slave.
INTSBI interrupt
if MST = 0
Then shift to the process when slave mode
if TRX = 0
Then shift to the process when receiver mode.
if LRB = 0
Then shift to the process that generates stop condition.
Check the <MST> by the INTSBI interrupt process after the 1-word data transfer is
When the <TRX> = “1” (Transmitter mode)
SBICR1
SBIDBR
End of interrupt
Note: X: Don’t care
Write to SBIDBR
D7
Implement the process to generate a stop condition (Refer to 3.15.6 (4)) and
terminate data transfer.
When the <LRB> is “0”, the receiver is requests new data. When the next
transmitted data is 8 bits, write the transmitted data to SBIDBR. When the next
transmitted data is other than 8 bits, set the <BC2:0> <ACK> and write the
transmitted data to SBIDBR. After written the data, <PIN> becomes “1”, a serial
clock pulse is generated for transferring a new 1-word of data from the SCL pin,
and then the 1-word data is transmitted. After the data is transmitted, an INTSBI
interrupt request occurs. The <PIN> becomes “0” and the SCL line is pulled down
to the Low-level. If the data to be transferred is more than one word in length,
repeat the procedure from the <LRB> checking above.
a.
1
Check the <TRX> and determine whether the mode is a transmitter or receiver.
Check the <LRB>. When <LRB> is “1”, a receiver does not request data.
If <MST> = “1” (Master Mode)
D6
← X X X X X X X X
← X X X X X X X X
2
7 6 5 4 3 2 1 0
D5
3
92CF26A-360
D4
4
D3
5
Set the bit number of transmit and ACK.
Write the transmit data.
D2
6
D1
7
D0
8
ACK
9
Acknowledge
signal from a
receiver
TMP92CF26A
2009-06-25