TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 535

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDVSP
(028CH)
(028DH)
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
TFT
STN
of the value set in LCDVSP<LV9:0> and the LHSYNC period.
Common size + number of dummy clocks
Common size + number of dummy clocks
(A minimum of one dummy clock must be inserted in the back porch.)
LVSYNC [s: period]
The period of the vertical synchronization signal LVSYNC is defined as the product
The value to be set in LCDVSP<LV9:0> is obtained as follows:
LVP7
7
7
0
LVP6
6
6
0
LCD LVSYNC Pulse Register
92CF26A-533
LVP5
= LHSYNC [s: period] × (<LV9:0> + 1)
= LCP0 [s: period] × (<LH15:0> + 1) × (<LV9:0> + 1)
5
5
0
LVSYNC period (bits 7-0)
LVP4
4
4
0
W
(*)
(*)
LVP3
3
3
0
LVP2
2
2
0
LVP1
LVP9
LVSYNC period
1
1
0
0
(bits 9-8)
TMP92CF26A
W
2009-06-25
LVP0
LVP8
0
0
0
0