TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 332

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SC0CR
(1201H)
A read
-modify-write
operation
cannot be
performed
bit Symbol
Read/Write
Reset State
Function
Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction.
Received
data bit 8
Undefined
RB8
R
7
Figure 3.14.7 Serial Control Register (channel 0, SC0CR)
Parity
0: odd
1: even
EVEN
6
0
R/W
Parity
addition
0: disable
1: enable
PE
5
0
92CF26A-330
Overrun
OERR
4
R (cleared to 0 when read)
0
1: error
PERR
Parity
3
0
Edge selection for SCLK pin (Input / Output Mode)
I/O interface input clock selection
Framing Error flag
Parity Error flag
Overrun Error flag
Framing
0
1
0
1
Parity addition enables
Even parity addition/check
Received data 8
FERR
0
1
0
1
2
0
Baud rate generator
SCLK0 pin input
Transmits and receives
data on rising edge of SCLK0.
Transmits and receives
data on falling edge SCLK0.
Disabled
Enabled
Odd parity
Even parity
0: SCLK0
1: SCLK0
SCLKS
1
0
R/W
0: baud rate
1: SCLK0
TMP92CF26A
generator
pin input
IOC
0
2009-06-25
0
Cleared to 0
when read