MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 107

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Figure 11. Clock tree
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
2. For full details about the internal and external clock source characteristics, please refer to the “Electrical
The advanced clock controller features 3 PLLs to provide a high degree of flexibility to the
application in the choice of the external crystal or oscillator to run the core and peripherals
at the highest frequency and guarantee the appropriate frequency for the Ethernet and USB
OTG FS.
A single 25 MHz crystal can clock the entire system and all peripherals including the
Ethernet and USB OTG FS peripherals. In order to achieve high-quality audio performance,
an audio crystal can be used. In this case, the I2S master clock can generate all standard
sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy.
For more details about clock configuration for applications requiring Ethernet, USB OTG FS
and/or I
connectivity line device datasheet.
36 MHz.
characteristics” section in your device datasheet.
ETH_MII_RX_CLK
ETH_MII_TX_CLK
2
OSC32_OUT
OSC_OUT
Ethernet
PHY
OSC32_IN
S (audio), please refer to "Appendix A Applicative block diagrams" in your
OSC_IN
MCO
XT1 to MCO
32.768 kHz
3-25 MHz
40 kHz
HSE
OSC
OSC
LSI
RC
LSE
MCO[3:0]
/2, /20
PREDIV2
/1,2,3....
..../15, /16
PREDIV1SCR
8 MHz
HSI RC
/128
HSE
HSI
PLLCLK/2
PLL2CLK
PLL3CLK/2
PLL3CLK
XT1
to Flash prog. IF
LSI
LSE
72 MHz max.
(see note1)
SYSCLK
RTCSEL[1:0]
PREDIV1
/1,2,3....
..../15, /16
MII_RMII_SEL
in AFIO_MAPR
/2
Doc ID 13902 Rev 9
Connectivity line devices: reset and clock control (RCC)
x8, x9,... x14,
x16, x20
x8, x9,... x14,
x16, x20
PLL3MUL
PLL2MUL
RTCCLK
to RTC
MACRMIICLK
MACRXCLK
MACTXCLK
IWDGCLK
to independent watchdog
PLLSCR
FLITFCLK
AHB prescaler
/1,/2 ../512
PLL2CLK
to MCO
PLLMUL
x4, x5,... x9,
x6.5
PLL3VCO
to Ethernet MAC
PLLVCO
USB prescaler
/2,3
PLL3CLK to MCO
PLLCLK
HSE
HSI
to USB OTG FS
OTGFSCLK
APB1 prescaler
/1, 2, 4, 8, 16
APB2 prescaler
/1, 2, 4, 8, 16
48 MHz
CSS
SW
to I2S2 interface
to I2S3 interface
/2
Peripheral clock enable
Peripheral clock enable
HCLK to AHB bus, core memory and DMA
TIM2,3,4,5,6,7
If(APB1 prescaler =1) x1
else x2
TIM1
If(APB2 prescaler =1) x1
else x2
ADC prescaler
/2, 4, 6, 8
36 MHz max
72 MHz max
Peripheral clock enable
Peripheral clock enable
SYSCLK
system clock
FCLK Cortex free running clock
to Cortex System timer
14 MHz max
ADCCLK
PCLK1
to APB1 peripherals
PCLK2
to APB2 peripherals
to TIM2,3,4,5,
TIMxCLK
TIMxCLK
to TIM1
to ADC1,2
6 & 7
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