MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 97

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
6.3.8
Note:
SPI3
EN
31
15
rw
Reserved
Res.
SPI2
EN
30
14
rw
Bits 31:30
APB1 peripheral clock enable register (RCC_APB1ENR)
Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
Bit 29 DACEN: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Bit 27 BKPEN: Backup interface clock enable
Bit 26
Bit 25 CANEN: CAN clock enable
Bit 24
Bit 23 USBEN: USB clock enable
DAC
EN
29
13
rw
Reserved
Res.
PWR
EN
28
rw
12
Reserved, always read as 0.
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Set and cleared by software.
0: Backup interface clock disabled
1: Backup interface clock enabled
Reserved, always read as 0.
Set and cleared by software.
0: CAN clock disabled
1: CAN clock enabled
Reserved, always read as 0.
Set and cleared by software.
0: USB clock disabled
1: USB clock enabled
WWD
GEN
BKP
EN
27
rw
11
rw
Res.
Res.
26
10
Low-, medium- and high-density reset and clock control (RCC)
CAN
EN
25
rw
9
Reserved
Doc ID 13902 Rev 9
Res.
Res.
Res.
24
8
USB
EN
23
rw
7
I2C2
EN
22
rw
6
TIM7
I2C1
EN
EN
21
rw
rw
5
UART5E
TIM6
EN
20
rw
rw
N
4
UART4
TIM5
EN
EN
19
rw
rw
3
USART
TIM4
3EN
EN
18
rw
rw
2
USART
TIM3
2EN
EN
17
rw
rw
1
97/995
TIM2
Res.
Res.
EN
16
rw
0