MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 899

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Bit 15 ES: Error summary
Bit 14 DE: Descriptor error
Bit 13 SAF: Source address filter fail
Bit 12 LE: Length error
Bit 10 VLAN: VLAN tag
Bit 11 OE: Overflow error
Bit 9 FS: First descriptor
Bit 8 LS: Last descriptor
Bit 7 IPHCE: IPv header checksum error
Bit 6 LCO: Late collision
Bit 5 FT: Frame type
Bit 4 RWT: Receive watchdog timeout
Indicates the logical OR of the following bits:
– RDES0[1]: CRC error
– RDES0[3]: Receive error
– RDES0[4]: Watchdog timeout
– RDES0[6]: Late collision
– RDES0[7]: Giant frame (This is not applicable when RDES0[7] indicates an IPV4 header
– RDES0[11]: Overflow error
– RDES0[14]: Descriptor error.
This field is valid only when the last descriptor (RDES0[8]) is set.
When set, this bit indicates a frame truncation caused by a frame that does not fit within the current
descriptor buffers, and that the DMA does not own the next descriptor. The frame is truncated. This
field is valid only when the last descriptor (RDES0[8]) is set.
When set, this bit indicates that the SA field of frame failed the SA filter in the MAC Core.
When set, this bit indicates that the actual length of the received frame does not match the value in
the Length/ Type field. This bit is valid only when the Frame type (RDES0[5]) bit is reset.
When set, this bit indicates that the received frame was damaged due to buffer overflow.
When set, this bit indicates that the frame pointed to by this descriptor is a VLAN frame tagged by
the MAC core.
When set, this bit indicates that this descriptor contains the first buffer of the frame. If the size of the
first buffer is 0, the second buffer contains the beginning of the frame. If the size of the second buffer is
also 0, the next descriptor contains the beginning of the frame.
When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of
the frame.
If IPHCE is set, it indicates an error in the IPv4 or IPv6 header. This error can be due to inconsistent
Ethernet Type field and IP header Version field values, a header checksum mismatch in IPv4, or an
Ethernet frame lacking the expected number of IP header bytes.
When set, this bit indicates that a late collision has occurred while receiving the frame in Half-
duplex mode.
When set, this bit indicates that the Receive frame is an Ethernet-type frame (the LT field is greater
than or equal to 0x0600). When this bit is reset, it indicates that the received frame is an IEEE802.3
frame. This bit is not valid for Runt frames less than 14 bytes.
When set, this bit indicates that the Receive watchdog timer has expired while receiving the
current frame and the current frame is truncated after the watchdog timeout.
checksum error.)
Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 9
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