MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 468

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Secure digital input/output interface (SDIO)
Note:
468/995
The DPSM remains in the Wait_S state for at least two clock periods to meet the N
requirements, where N
response and the start of the data transfer from the host.
●
●
●
Table 125. Data token format
Data FIFO
The data FIFO (first-in-first-out) subunit is a data buffer with a transmit and receive unit.
The FIFO contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic.
Because the data FIFO operates in the AHB clock domain (HCLK/2), all signals from the
subunits in the SDIO clock domain (SDIOCLK) are resynchronized.
Block Data
Stream Data
Description
Send: the DPSM starts sending data to a card. Depending on the transfer mode bit in
the data control register, the data transfer mode can be either block or stream:
–
–
If a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the
Idle state.
Busy: the DPSM waits for the CRC status flag:
–
–
If a timeout occurs while the DPSM is in the Busy state, it sets the data timeout flag and
moves to the Idle state.
The data timer is enabled when the DPSM is in the Wait_R or Busy state, and
generates the data timeout error:
–
–
Data: data can be transferred from the card to the host or vice versa. Data is
transferred via the data lines
bits wide.
In block mode, when the data block counter reaches zero, the DPSM sends an
internally generated CRC code and end bit, and moves to the Busy state.
In stream mode, the DPSM sends data to a card while the enable bit is high and
the data counter is not zero. It then moves to the Idle state.
If it does not receive a positive CRC status, it moves to the Idle state and sets the
CRC fail status flag.
If it receives a positive CRC status, it moves to the Wait_S state if SDIO_D0 is not
low (the card is not busy).
When transmitting data, the timeout occurs if the DPSM stays in the Busy state for
longer than the programmed timeout period
When receiving data, the timeout occurs if the end of the data is not true, and if the
DPSM stays in the Wait_R state for longer than the programmed timeout period.
0
0
WR
Start bit
is the number of clock cycles between the reception of the card
Doc ID 13902 Rev 9
.
They are stored in a FIFO of 32 words
-
-
Data
yes
no
CRC16
,
each word is 32
1
1
End bit
WR
RM0008
timing