MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 943

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
The Ethernet interrupt is generated only when the TSTS or PMTS bits of the DMA Status
register is asserted with their corresponding interrupt are unmasked, or when the NIS/AIS
Status bit is asserted and the corresponding Interrupt Enable bits (NISE/AISE) are enabled.
Bit 9 RWTIE: receive watchdog timeout interrupt enable
Bit 8 RPSIE: Receive process stopped interrupt enable
Bit 7 RBUIE: Receive buffer unavailable interrupt enable
Bit 6 RIE: Receive interrupt enable
Bit 5 TUIE: Underflow interrupt enable
Bit 4 ROIE: Overflow interrupt enable
Bit 3 TJTIE: Transmit jabber timeout interrupt enable
Bit 2 TBUIE: Transmit buffer unavailable interrupt enable
Bit 1 TPSIE: Transmit process stopped interrupt enable
Bit 0 TIE: Transmit interrupt enable
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER
register[15]), the receive watchdog timeout interrupt is enabled.
When this bit is cleared, the receive watchdog timeout interrupt is disabled.
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER
register[15]), the receive stopped interrupt is enabled. When this bit is cleared, the receive
stopped interrupt is disabled.
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER
register[15]), the receive buffer unavailable interrupt is enabled.
When this bit is cleared, the receive buffer unavailable interrupt is disabled.
When this bit is set with the normal interrupt summary enable bit (ETH_DMAIER register[16]),
the receive interrupt is enabled.
When this bit is cleared, the receive interrupt is disabled.
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER
register[15]), the transmit underflow interrupt is enabled.
When this bit is cleared, the underflow interrupt is disabled.
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER
register[15]), the receive overflow interrupt is enabled.
When this bit is cleared, the overflow interrupt is disabled.
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER
register[15]), the transmit jabber timeout interrupt is enabled.
When this bit is cleared, the transmit jabber timeout interrupt is disabled.
When this bit is set with the normal interrupt summary enable bit (ETH_DMAIER register[16]),
the transmit buffer unavailable interrupt is enabled.
When this bit is cleared, the transmit buffer unavailable interrupt is disabled.
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER
register[15]), the transmission stopped interrupt is enabled.
When this bit is cleared, the transmission stopped interrupt is disabled.
When this bit is set with the normal interrupt summary enable bit (ETH_DMAIER register[16]),
the transmit interrupt is enabled.
When this bit is cleared, the transmit interrupt is disabled.
Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 9
943/995