MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 683

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
25.6
25.6.1
31
15
30
14
Bits 31:10 Reserved, forced by hardware to 0.
USART registers
Refer to
Status register (USART_SR)
Address offset: 0x00
Reset value: 0x00C0
Bit 9 CTS: CTS flag
Bit 8 LBD: LIN break detection flag
Bit 7 TXE: Transmit data register empty
Bit 6 TC: Transmission complete
29
13
Reserved
Res.
Note: This bit is not available for UART4 & UART5.
Note: An interrupt is generated when LBD=1 if LBDIE=1
Note: This bit is used during single buffer transmission.
Section 1.1 on page 37
This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared
by software (by writing it to 0). An interrupt is generated if CTSIE=1 in the USART_CR3
register.
0: No change occurred on the nCTS status line
1: A change occurred on the nCTS status line
This bit is set by hardware when the LIN break is detected. It is cleared by software (by
writing it to 0). An interrupt is generated if LBDIE = 1 in the USART_CR2 register.
0: LIN Break not detected
1: LIN break detected
This bit is set by hardware when the content of the TDR register has been transferred into
the shift register. An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. It
is cleared by a write to the USART_DR register.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register)
This bit is set by hardware if the transmission of a frame containing data is complete and if
TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by a
software sequence (a read from the USART_SR register followed by a write to the
USART_DR register). The TC bit can also be cleared by writing a '0' to it. This clearing
sequence is recommended only for multibuffer communication.
0: Transmission is not complete
1: Transmission is complete
28
12
27
11
Universal synchronous asynchronous receiver transmitter (USART)
26
10
rc_w0
CTS
25
9
Doc ID 13902 Rev 9
for a list of abbreviations used in register descriptions.
rc_w0
LBD
24
8
Reserved
TXE
23
7
r
rc_w0
TC
22
6
RXNE
rc_w0
21
5
IDLE
20
4
r
ORE
19
3
r
NE
18
2
r
FE
17
1
r
683/995
PE
16
0
r