MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 267

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
13.3.4
Clock selection
The counter clock can be provided by the following clock sources:
●
●
●
●
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 72
without prescaler.
Figure 72. Control circuit in normal mode, internal clock divided by 1
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count
at each rising or falling edge on a selected input.
Figure 73. TI2 external clock connection example
Internal clock (CK_INT)
External clock mode1: external input pin
External clock mode2: external trigger input ETR
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to
Using one timer as prescaler for another timer on page 353
TI2
shows the behavior of the control circuit and the upcounter in normal mode,
Counter clock = CK_CNT = CK_PSC
TIMx_CCMR1
ICF[3:0]
Filter
Detector
Edge
CEN=CNT_EN
Counter register
Internal clock
TI2F_Rising
TI2F_Falling
CNT_INIT
Doc ID 13902 Rev 9
UG
TIMx_CCER
CC2P
0
1
31
TI1_ED
TI1FP1
TI2FP2
ETRF
ITRx
32 33 34 35 36
TIMx_SMCR
TS[2:0]
100
101
110
111
0xx
Advanced-control timers (TIM1&TIM8)
or
(internal clock)
CK_INT
TI1F
TI2F
TRGI
ETRF
00
or
or
01 02 03 04 05 06 07
ECE
for more details.
encoder
mode
external clock
mode 1
external clock
mode 2
internal clock
mode
TIMx_SMCR
SMS[2:0]
CK_PSC
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