MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 549

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
22.6
22.7
22.7.1
Figure 197. bxCAN in combined mode
STM32F10xxx in Debug mode
When the microcontroller enters the debug mode (Cortex-M3 core halted), the bxCAN
continues to work normally or stops, depending on:
●
●
bxCAN functional description
Transmission handling
In order to transmit a message, the application must select one empty transmit mailbox, set
up the identifier, the data length code (DLC) and the data before requesting the transmission
by setting the corresponding TXRQ bit in the CAN_TIxR register. Once the mailbox has left
empty state, the software no longer has write access to the mailbox registers. Immediately
after the TXRQ bit has been set, the mailbox enters pending state and waits to become the
highest priority mailbox, see Transmit Priority. As soon as the mailbox has the highest
priority it will be scheduled for transmission. The transmission of the message of the
scheduled mailbox will start (enter transmit state) when the CAN bus becomes idle. Once
the mailbox has been successfully transmitted, it will become empty again. The hardware
indicates a successful transmission by setting the RQCP and TXOK bits in the CAN_TSR
register.
If the transmission fails, the cause is indicated by the ALST bit in the CAN_TSR register in
case of an Arbitration Lost, and/or the TERR bit, in case of transmission error detection.
Transmit priority
By identifier:
When more than one transmit mailbox is pending, the transmission order is given by the
identifier of the message stored in the mailbox. The message with the lowest identifier value
has the highest priority according to the arbitration of the CAN protocol. If the identifier
values are equal, the lower mailbox number will be scheduled first.
By transmit request order:
the DBG_CAN1_STOP bit for CAN1 or the DBG_CAN2_STOP bit for CAN2 in the DBG
module. For more details, refer to
bxCAN and I
the DBF bit in CAN_MCR. For more details, refer to
status
registers.
2
C.
Doc ID 13902 Rev 9
bxCAN
Section 29.16.2: Debug support for timers, watchdog,
CANTX CANRX
Tx
=1
Rx
Controller area network (bxCAN)
Section 22.9.2: CAN control and
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