MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 759
MCBSTM32EXL
Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Specifications of MCBSTM32EXL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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RM0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Bits 31:16 OEPINT: OUT endpoint interrupt bits
Bits 15:0 IEPINT: IN endpoint interrupt bits
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OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
Address offset: 0x818
Reset value: 0x0000 0000
When a significant event occurs on an endpoint, a Device all endpoints interrupt register
interrupts the application using the Device OUT endpoints interrupt bit or Device IN
endpoints interrupt bit of the Core interrupt register (OEPINT or IEPINT in
OTG_FS_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum
of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the
corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared
when the application sets and clears bits in the corresponding Device Endpoint-x interrupt
register (OTG_FS_DIEPINTx/OTG_FS_DOEPINTx).
Bit 6 B2BSTUP: Back-to-back SETUP packets received mask
Bit 5 Reserved
Bit 4 OTEPDM: OUT token received when endpoint disabled mask
Bit 3 STUPM: SETUP phase done mask
Bit 2 Reserved
Bit 1 EPDM: Endpoint disabled interrupt mask
Bit 0 XFRCM: Transfer completed interrupt mask
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One bit per OUT endpoint:
Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15
One bit per IN endpoint:
Bit 0 for IN endpoint 0, bit 15 for endpoint 15
Applies to control OUT endpoints only.
Applies to control OUT endpoints only.
Applies to control endpoints only.
r
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
OEPINT
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Doc ID 13902 Rev 9
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USB on-the-go full-speed (OTG_FS)
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9
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IEPINT
8
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7
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6
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5
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4
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3
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2
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759/995
1
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0
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