MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 989

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Table 215. Document revision history (continued)
23-Dec-2008
Date
Revision
7
Memory map figure removed from reference manual.
architecture on page 38
page 48
RTC calibration on page 67
page 175
Section 6.3: RCC registers on page 82
features on page 182
Section 10.3.5: Error management
in connectivity line devices on page 183
Programmable data width, data alignment and endians on page 186
Bit definition modified in
register (DMA_CPARx) (x = 1 ..7) on page 195
channel x memory address register (DMA_CMARx) (x = 1 ..7) on page
Note added below
input mode
FSMC_NWAIT signal direction corrected in
page
Value to set modified for bit 6 in
FSMC_BCRx bit fields
bit NAND
Card
Card. Note added in PWAITEN bit definition in
registers 2..4 (FSMC_PCR2..4) on page
Bit definitions updated in
(FSMC_SR2..4) on page
definitions in
(FSMC_BTR1..4) on page
control registers 2..4 (FSMC_PCR2..4) on page
MEMWAIT[15:8] bit definition modified in
register 2..4 (FSMC_PMEM2..4) on page
ATTWAIT[15:8] bit definition modified in
registers 2..4 (FSMC_PATT2..4) on page
Section 19.6.5: NAND Flash pre-wait functionality on page 446
Figure 175: NAND/PC Card controller timing for common memory access
modified.
Note added below
32-bit external memory access removed from
address on page 412
Caution:
page
NIOS16 description modified in
Register description modified in
(FSMC_PATT2..4) on page
Resetting the password on page 478
write_data signal modified in
for common memory
bxCAN main features on page 542
Section 24.3.8: Packet error checking on page 639
Section 29.6.3: Cortex-M3 TAP
DBG_TIMx_STOP positions modified in
Small text changes.
modified. NWAIT and INTR signals separated in
410.
442.
Doc ID 13902 Rev 9
modified.
added to
updated.
Flash,
timing.
SRAM/NOR-Flash chip-select timing registers 1..4
Table 115: 16-bit NAND Flash
Figure 81: PWM input mode timing
Section 19.6.1: External memory interface signals on
Exiting Sleep mode on page 58
Table 84: NOR/PSRAM bank selection on page
access.
and note added.
updated.
and
modified.
Section 10.4.5: DMA channel x peripheral address
FIFO status and interrupt register 2..4
449. Note modified in ADDHLD and ADDSET bit
438. Bit 8 is reserved in
Table 107: FSMC_BCRx bit
451.
updated.
Figure 175: NAND/PC Card controller timing
Table 98: FSMC_BCRx bit
modified.
Table 116: 16-bit PC Card on page
Attribute memory space timing registers 2..4
Changes
Section 2.4: Boot configuration on
modified.
modified.
step 2 corrected.
Wakeup event management on
updated.
Attribute memory space timing
DBGMCU_CR on page
modified.
448.
Common memory space timing
451.
450.
Figure 19.3: AHB interface on
Figure 22: DMA block diagram
Table 85: External memory
PC Card/NAND Flash control
and
448.
and
Section 10.2: DMA main
Section 10.3.4:
modified.
PC Card/NAND Flash
modified.
Section 10.4.6: DMA
Table 116: 16-bit PC
Section 2.1: System
and
Table 116: 16-bit PC
fields.
Revision history
Figure 127: PWM
fields,
Section 5.3.2:
Table 114: 8-
modified.
972.
Table 101:
412.
443.
989/995
added.
195.