MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 88

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low-, medium- and high-density reset and clock control (RCC)
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Bits 15:13
Bits 6:5
Bit 17 LSERDYC: LSE ready interrupt clear
Bit 16 LSIRDYC: LSI ready interrupt clear
Bit 12 PLLRDYIE: PLL ready interrupt enable
Bit 11 HSERDYIE: HSE ready interrupt enable
Bit 10 HSIRDYIE: HSI ready interrupt enable
Bit 9 LSERDYIE: LSE ready interrupt enable
Bit 8 LSIRDYIE: LSI ready interrupt enable
Bit 7 CSSF: Clock security system interrupt flag
Bit 4 PLLRDYF: PLL ready interrupt flag
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
Reserved, always read as 0.
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the external 4-25 MHz
oscillator stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC
oscillator stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the external 32 kHz
oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz
oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Set by hardware when a failure is detected in the external 4-25 MHz oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Reserved, always read as 0.
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Doc ID 13902 Rev 9
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