MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 116

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Connectivity line devices: reset and clock control (RCC)
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Bits 26:24 MCO[3:0]: Microcontroller clock output
Bits 21:18 PLLMUL[3:0]: PLL multiplication factor
Bit 22 OTGFSPRE: USB OTG FS prescaler
Bit 17 PLLXTPRE: LSB of division factor PREDIV1
Bit 16 PLLSRC: PLL entry clock source
Note: This clock output may have some truncated cycles at startup or during MCO clock source
Caution: The PLL output frequency must not exceed 72 MHz.
Note: When changing the main PLL’s entry clock source, the original clock source must be switched
Set and cleared by software.
00xx: No clock
0100: System clock (SYSCLK) selected
0101: HSI clock selected
0110: HSE clock selected
0111: PLL clock divided by 2 selected
1000: PLL2 clock selected
1001: PLL3 clock divided by 2 selected
1010: XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
1011: PLL3 clock selected (for Ethernet)
Set and cleared by software to generate the 48 MHz USB OTG FS clock. This bit must be valid
before enabling the OTG FS clock in the RCC_APB1ENR register. This bit can not be cleared if the
OTG FS clock is enabled.
0: PLL VCO clock is divided by 3
1: PLL VCO clock is divided by 2
These bits are written by software to define the PLL multiplication factor. They can be written only
when PLL is disabled.
000x: Reserved
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
10xx: Reserved
1100: Reserved
1101: PLL input clock x 6.5
111x: Reserved
Set and cleared by software to select the least significant bit of the PREDIV1 division factor. It is the
same bit as bit(0) in the RCC_CFGR2 register, so modifying bit(0) in the RCC_CFGR2 register
changes this bit accordingly.
If bits[3:1] in register RCC_CFGR2 are not set, this bit controls if PREDIV1 divides its input clock by
2 (PLLXTPRE=1) or not (PLLXTPRE=0).
This bit can be written only when PLL is disabled.
Set and cleared by software to select PLL clock source. This bit can be written only when PLL is
disabled.
0: HSI oscillator clock / 2 selected as PLL input clock
1: Clock from PREDIV1 selected as PLL input clock
switching.
The selected clock to output onto the MCO pin must not exceed 50 MHz (the maximum I/O
speed).
off only after the selection of the new clock source.
Doc ID 13902 Rev 9
RM0008