MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 165

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
8.4.3
8.4.4
31
15
rw
31
15
rw
30
14
30
14
Bits 31:16
rw
rw
EXTI3[3:0]
Bits 31:16
EXTI7[3:0]
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 4 to 7)
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3)
External interrupt configuration register 1 (AFIO_EXTICR1)
Address offset: 0x08
Reset value: 0x0000
External interrupt configuration register 2 (AFIO_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000
Bit 0 SPI1_REMAP: SPI1 remapping
29
13
rw
29
13
rw
Reserved
These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO,
MOSI alternate functions on the GPIO ports.
0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
Reserved
These bits are written by software to select the source input for EXTIx external interrupt.
Refer to
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
28
12
rw
28
12
rw
27
11
27
11
rw
rw
Section 9.2.5: External interrupt/event line mapping on page 176
26
10
rw
26
10
rw
EXTI2[3:0]
EXTI6[3:0]
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
25
rw
25
rw
9
9
Doc ID 13902 Rev 9
24
24
rw
rw
8
8
Reserved
Reserved
23
rw
23
rw
7
7
22
rw
22
rw
EXTI1[3:0]
EXTI5[3:0]
6
6
21
21
rw
rw
5
5
20
20
rw
rw
4
4
19
rw
19
rw
3
3
18
18
rw
rw
2
EXTI0[3:0]
2
EXTI4[3:0]
17
17
rw
rw
1
1
165/995
16
rw
16
rw
0
0