MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 685

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
25.6.2
31
15
30
14
Bits 31:9 Reserved, forced by hardware to 0.
Bits 8:0 DR[8:0]: Data value
Data register (USART_DR)
Address offset: 0x04
Reset value: Undefined
Bit 0 PE: Parity error
29
13
Reserved
Res.
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a
software sequence (a read to the status register followed by a read to the USART_DR data
register). The software must wait for the RXNE flag to be set before clearing the PE bit.
An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0: No parity error
1: Parity error
Contains the Received or Transmitted data character, depending on whether it is read from
or written to.
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR)
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 1).
The RDR register provides the parallel interface between the input shift register and the
internal bus.
When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the
value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because
it is replaced by the parity.
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.
28
12
27
11
Universal synchronous asynchronous receiver transmitter (USART)
26
10
25
9
Doc ID 13902 Rev 9
24
rw
8
Reserved
23
rw
7
22
rw
6
21
rw
5
DR[8:0]
20
rw
4
19
rw
3
18
rw
2
17
rw
1
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16
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0