MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 388

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Real-time clock (RTC)
16.2
16.3
16.3.1
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RTC main features
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RTC functional description
Overview
The RTC consists of two main units (see
Interface) is used to interface with the APB1 bus. This unit also contains a set of 16-bit
registers accessible from the APB1 bus in read or write mode (for more information refer to
Section 16.4: RTC registers on page
clock in order to interface with the APB1 bus.
The other unit (RTC Core) consists of a chain of programmable counters made of two main
blocks. The first block is the RTC prescaler block, which generates the RTC time base
TR_CLK that can be programmed to have a period of up to 1 second. It includes a 20-bit
programmable divider (RTC Prescaler). Every TR_CLK period, the RTC generates an
interrupt (Second Interrupt) if it is enabled in the RTC_CR register. The second block is a
32-bit programmable counter that can be initialized to the current system time. The system
time is incremented at the TR_CLK rate and compared with a programmable date (stored in
the RTC_ALR register) in order to generate an alarm interrupt, if enabled in the RTC_CR
control register.
Programmable prescaler: division factor up to 2
32-bit programmable counter for long-term measurement
Two separate clocks: PCLK1 for the APB1 interface and RTC clock (must be at least
four times slower than the PCLK1 clock)
The RTC clock source could be any of the following three:
–
–
–
Two separate reset types:
–
–
Three dedicated maskable interrupt lines:
–
–
–
HSE clock divided by 128
LSE oscillator clock
LSI oscillator clock (refer to
The APB1 interface is reset by system reset
The RTC Core (Prescaler, Alarm, Counter and Divider) is reset only by a Backup
domain reset (see
Alarm interrupt, for generating a software programmable alarm interrupt.
Seconds interrupt, for generating a periodic interrupt signal with a programmable
period length (up to 1 second).
Overflow interrupt, to detect when the internal programmable counter rolls over to
zero.
Section 6.1.3: Backup domain reset on page
Doc ID 13902 Rev 9
392). The APB1 interface is clocked by the APB1 bus
Section 6.2.8: RTC clock
Figure 155 on page
20
389). The first one (APB1
for details)
75).
RM0008