MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 269

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
13.3.5
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1.
2.
3.
4.
5.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 76. Control circuit in external clock mode 2
Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 77
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
to
Counter clock = CK_CNT = CK_PSC
Figure 80
give an overview of one Capture/Compare channel.
Counter register
CNT_EN
Doc ID 13902 Rev 9
f
CK_INT
ETRP
ETRF
ETR
34
Advanced-control timers (TIM1&TIM8)
35
36
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