MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 151

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
8.2.6
8.2.7
LCK15
BR15
31
15
31
15
rw
w
LCK14
BR14
30
14
30
14
Bits 31:17
Bits 31:16
rw
w
Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15)
Port bit reset register (GPIOx_BRR) (x=A..G)
Address offset: 0x14
Reset value: 0x0000 0000
Port configuration lock register (GPIOx_LCKR) (x=A..G)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit it is no longer possible to modify the value of
the port bit until the next reset.
Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH).
Address offset: 0x18
Reset value: 0x0000 0000
LCK13
BR13
29
13
29
13
rw
w
LCK12
BR12
Reserved
Reserved
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
28
12
28
12
rw
w
LCK11
BR11
27
11
27
11
rw
w
LCK10
BR10
26
10
26
10
rw
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
w
LCK9
BR9
25
25
rw
w
9
9
Doc ID 13902 Rev 9
Reserved
LCK8
BR8
24
24
Reserved
rw
w
8
8
LCK7
BR7
23
23
rw
w
7
7
LCK6
BR6
22
22
rw
w
6
6
LCK5
BR5
21
21
rw
w
5
5
LCK4
BR4
20
20
rw
w
4
4
LCK3
BR3
19
19
rw
w
3
3
LCK2
BR2
18
18
rw
w
2
2
LCK1
BR1
17
17
rw
w
1
1
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LCKK
LCK0
BR0
16
16
rw
rw
w
0
0