MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 938

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
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Bit 8 RPSS: Receive process stopped status
Bit 7 RBUS: Receive buffer unavailable status
Bit 6 RS: Receive status
Bit 5 TUS: Transmit underflow status
Bit 4 ROS: Receive overflow status
Bit 3 TJTS: Transmit jabber timeout status
Bit 2 TBUS: Transmit buffer unavailable status
Bit 1 TPSS: Transmit process stopped status
Bit 0 TS: Transmit status
This bit is asserted when the receive process enters the Stopped state.
This bit indicates that the next descriptor in the receive list is owned by the host and cannot be
acquired by the DMA. Receive process is suspended. To resume processing receive
descriptors, the host should change the ownership of the descriptor and issue a Receive Poll
Demand command. If no Receive Poll Demand is issued, receive process resumes when the
next recognized incoming frame is received. ETH_DMASR [7] is set only when the previous
receive descriptor was owned by the DMA.
This bit indicates the completion of the frame reception. Specific frame status information has
been posted in the descriptor. Reception remains in the Running state.
This bit indicates that the transmit buffer had an underflow during frame transmission.
Transmission is suspended and an underflow error TDES0[1] is set.
This bit indicates that the receive buffer had an overflow during frame reception. If the partial
frame is transferred to the application, the overflow status is set in RDES0[11].
This bit indicates that the transmit jabber timer expired, meaning that the transmitter had been
excessively active. The transmission process is aborted and placed in the Stopped state. This
causes the transmit jabber timeout TDES0[14] flag to be asserted.
This bit indicates that the next descriptor in the transmit list is owned by the host and cannot be
acquired by the DMA. Transmission is suspended. Bits [22:20] explain the transmit process
state transitions. To resume processing transmit descriptors, the host should change the
ownership of the bit of the descriptor and then issue a Transmit Poll Demand command.
This bit is set when the transmission is stopped.
This bit indicates that frame transmission is finished and TDES1[31] is set in the first descriptor.
Doc ID 13902 Rev 9
RM0008