MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 892

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
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31 30 29 28 27 26 25
W
rw rw rw rw rw rw rw
O
N
IC LS FS DC DP
Bits 23:22 CIC: Checksum insertion control
●
Bit 31 OWN: Own bit
Bit 30 IC: Interrupt on completion
Bit 29 LS: Last segment
Bit 28 FS: First segment
Bit 27 DC: Disable CRC
Bit 26 DP: Disable pad
Bit 25 TTSE: Transmit time stamp enable
Bit 24 Reserved
Bit 21 TER: Transmit end of ring
TDES0: Transmit descriptor Word0: Transmit time stamp control and status
The value of this field should be preserved by the DMA at the time of closing the
descriptor.
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it
indicates that the descriptor is owned by the CPU. The DMA clears this bit either when it
completes the frame transmission or when the buffers allocated in the descriptor are read
completely. The ownership bit of the frame’s first descriptor must be set after all subsequent
descriptors belonging to the same frame have been set.
When set, this bit sets the Transmit Interrupt (Register 5[0]) after the present frame has been
transmitted.
When set, this bit indicates that the buffer contains the last segment of the frame.
When set, this bit indicates that the buffer contains the first segment of a frame.
When this bit is set, the MAC does not append a cyclic redundancy check (CRC) to the end of
the transmitted frame. This is valid only when the first segment (TDES0[28]) is set.
When set, the MAC does not automatically add padding to a frame shorter than 64 bytes.
When this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than
64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This is valid
only when the first segment (TDES0[28]) is set.
by the descriptor. This field is only valid when the First segment control bit (TDES0[28]) is set.
These bits control the checksum calculation and insertion. Bit encoding is as shown below:
This field is reserved when the IPC_FULL_OFFLOAD configuration parameter is not selected.
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns
to the base address of the list, creating a descriptor ring.
When set, this field enables IEEE1588 hardware time stamping for the transmit frame described
SE Res
TT
00: Checksum Insertion disabled
01: Only IP header checksum calculation and insertion are enabled
10: IP header checksum and payload checksum calculation and insertion are enabled, but
pseudo-header checksum is not calculated in hardware
11: IP Header checksum and payload checksum calculation and insertion are enabled, and
pseudo-header checksum is calculated in hardware.
24
23 22 21 20 19 18 17 16 15 14 13 12 11 10
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CIC
TE
R
TC
H
Res.
Doc ID 13902 Rev 9
TT
SS
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IH
E
ES JT FF
IP
E
LC
A
NC
LC
O
9
EC VF
8
7
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5
CC
4
3
ED UF DB
2
RM0008
1
0