MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 439

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Note:
Bits 15:8 DATAST: Data-phase duration
Bits 7:4 ADDHLD: Address-hold phase duration
Bits 3:0 ADDSET: Address setup phase duration
PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these
memories issue the NWAIT signal during the whole latency phase to prolong the latency as
needed.
With PSRAMs (CRAMs) the filed DATLAT must be set to 0, so that the FSMC exits its
latency phase soon and starts sampling NWAIT from memory, then starts to read or write
when the memory is ready.
This method can be used also with the latest generation of synchronous Flash memories
that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the
specific Flash memory being used).
Note: In synchronous accesses, this value is not used, the address hold phase is always 1
Note: In synchronous accesses, this value is not used, the address hold phase is always 1
These bits are written by software to define the duration of the data phase (refer to
Figure 162
accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 2 × HCLK clock cycles
0000 0010: DATAST phase duration = 3 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 256 × HCLK clock cycles (default value after reset)
For each memory type and access mode data-phase duration, please refer to the respective
figure
Example: Mode1, read access, DATAST=1: Data-phase duration= DATAST+3 = 4 HCLK
clock cycles.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 170
0000: Reserved
0001: ADDHLD phase duration = 2 × HCLK clock cycle
0010: ADDHLD phase duration = 3 × HCLK clock cycle
...
1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset)
For each access mode address-hold phase duration, please refer to the respective figure
(Figure 170
Example: ModeD, read access, ADDHLD=1: Address-hold phase duration = ADDHLD + 1 =2
HCLK clock cycles.
These bits are written by software to define the duration of the address setup phase (refer to
Figure 162
0000: ADDSET phase duration = 1 × HCLK clock cycle
...
1111: ADDSET phase duration = 16 × HCLK clock cycles (default value after reset)
For each access mode address setup phase duration, please refer to the respective figure
(refer to
Example: Mode2, read access, ADDSET=1: Address setup phase duration = ADDSET + 1 =
2 HCLK clock cycles.
memory clock period duration.
memory clock period duration.
(Figure 162
Figure 162
to
to
to
to
Figure
Figure
Figure
Figure
to
to
172), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash
Figure
172), used in mode D and multiplexed accesses:
172), used in SRAMs, ROMs and asynchronous NOR Flash:
172).
Figure
Doc ID 13902 Rev 9
172).
172).
Flexible static memory controller (FSMC)
439/995